If you have ordered controlled-impedance boards, you have seen 50 Ω, 90 Ω differential, ±10% on the quote. Those numbers are not abstract labels—they are process commitments from the fabricator tied to dielectric, copper weight, and geometry your PCB layout must match. When schematic capture names high-speed interfaces but the stack-up was never locked with the fab, you are planning layout without a shared definition of success—exactly the kind of cross-team gap that turns bring-up into guesswork.
What characteristic impedance means on a real trace
A trace is distributed L and C; at sufficient edge rates, energy propagates as a wave. Z0 is the ratio of voltage to current for that traveling wave—set by width, height to reference, Dk, and loss. Change Z0 along the route (neck-down, stub, via, connector) and part of the wave reflects—closing the eye at the receiver.
Single-ended vs differential—follow the standard
Single-ended lines often target 50 Ω where the interface demands it. Differential pairs target 90–100 Ω differential for many serialized buses—spacing and width together define both differential and common-mode behaviour. The IC vendor or standard wins, not generic blog defaults.
Stack-up is the contract
Impedance control starts with approved stack-ups: which layers are signal vs plane, prepreg vs core, and thickness/Dk. You map required Z0 to trace width/gap using field solvers that match your reference planes. Tolerance (often ±10%) is a cost and risk knob; coupons on the panel help when designs are marginal.
Where controlled impedance usually breaks
- Via stubs on very fast nets.
- Layer transitions without continuous return paths.
- Neck-downs into dense BGAs without simulation or vendor guidance.
- Connectors whose landing pattern diverges from reference layouts.
Verification before fab
Constraint manager rules, DRC for impedance regions, fab sign-off on stack-up and table, optional TDR on first article for risky channels.
When Haizom gets involved
Schematic capture and PCB design here means constraints and stack-up are decided while schematic changes are cheap—so SI risk is visible before placement is frozen. The goal is a package your CM can build and your team can revise without losing the thread from netlist to field behaviour.
Related search topics: PCB controlled impedance calculator, differential pair routing guidelines, via stub back drill PCB, stack-up documentation for fab, TDR impedance measurement coupon.
Tags
- PCB design
- Impedance
- High-speed PCB
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